The present invention relates to a clock distribution circuit for supplying a clock signal to a plurality of parts or circuitries incorporated in a large scale integrated circuit or LSI chip.
In conjunction with supply of clock signals to a number of circuitries incorporated in a LSI chip used in electronic computers and the like, there have heretofore been proposed a variety of approaches for making it possible to supply the clock signals to a number of internal circuitries while maintaining same phase among the clock signals. As a typical one of such approaches, there may be mentioned a technique disclosed in, for example, "1992 Symposium on VLSI Circuits Digest of Technical Papers", pp. 50-53, and ISSCC 92 SESSION 6/MICROPROCESSORS/PAPER TA6.2, PAPER TA6.3 and PAPER TA6.1. A clock signal supply system is disclosed in, for example, U.S. Pat. No. 5,184,027 issued on Feb. 2, 1993.
As the most popular intra-LSI clock distribution circuit, a distribution circuit of tree-like structure may be mentioned, which is comprised of a main distribution circuit disposed at an appropriate position within the LSI chip, e.g. at a center thereof, and a plurality of intra-block distribution circuitries disposed within a plurality of regions or blocks of a same size which result from division of the chip. The main distribution circuit receives a clock signal supplied externally of the chip and distributes the clock signal to a plurality of intra-block distribution circuitries via a plurality of wires having respective capacitances equal to one another. Each of the intra-block distribution circuitries in turn distributes again the received clock signal to a plurality of flip-flops, respectively, which are incorporated in the associated block via a plurality of wires having substantially same capacitance. In an LSI chip where a large number of flip-flops are provided in each block, a plurality of drivers are connected to the output of the intra-block clock distribution circuitries in a tree-like configuration, wherein the clock signal is supplied to associated one or plural flip-flops from the drivers of the final stage.
The intra-block distribution circuitry or the clock driver is implemented in a same structure common to all the blocks. By virtue of this arrangement, the delays which the clock signals experience in the course of traveling along the wires from the intra-block distribution circuitry to the individual flip-flops provided in each block can be equalized to one another, whereby clock skew is suppressed.
As another typical clock distribution circuit, there may be mentioned a net-like distribution circuit, which is comprised of wires provided over the whole chip in a mesh-like pattern and a group of drivers for supplying the clock signal to the wires, wherein the drivers are connected in a tree-like array having a multiplicity of stages, and the outputs of plural drivers belonging to a same stage are connected to one another, as is shown in FIG. 1 of the reference literature cited above. By decreasing sufficiently the resistance of the mesh-like wiring, difference in the timing of voltage changes brought about at various circuit points in the mesh by the clock signal can be suppressed to a negligible minimum. Thus, the flip-flops in the LSI to which the clock signal is to be supplied can be connected to the mesh at the appropriate positions located in the vicinity of the flip-flops.
Parenthetically, an inter-chip block distribution circuit for distributing clocks to a plurality of chips is also described in the aforementioned literature as well.
As another technique known heretofore, there may be mentioned one disclosed in JP-A-4-76610 filed in the name of the assignee of this application, according to which clocks are supplied in parallel to a plurality of blocks in an LSI chip, wherein a clock signal supplied to a representative one of the blocks is selected for phase-matching with the clock signals supplied to the blocks located in the periphery of the representative block. Besides, the clock signals for the peripheral blocks can also be utilized for the phase-matching of the clock signals supplied to the blocks located around the peripheral blocks.
In the clock distribution circuit of the tree configuration, it is necessary to equalize mutually the load capacitances of plural wires leading to the flip-flops from the clock distribution circuitry so that the delays which the clock signals undergo during traveling from the intra-block distribution circuitry to the plural flip-flops can be equalized. To this end, the wires are formed of a same material and so designed as to have respective lengths equal to one another.
In practical applications, however, very complicated design and troublesome manufacturing process are required in order to cancel out variance in the delay time among the clock signals. It is naturally expected that the problem becomes more serious as the scale of LSI increases further in the future.
By way of example, in the case of an LSI known as the gate array, a large number of elements having a same structure and referred to as the basic cells are incorporated, wherein interconnections of the cells can be changed in dependence on applications which the LSI chip can find. Thus, the LSI capable of performing various functions can be implemented by using one and the same LSI chip. In the case of this gate array, a great number of basic cells mentioned above are periodically disposed and divided into a plurality of blocks of a same size independent of intended applications of the LSI, wherein the intra-block clock distribution circuitry is previously included in each of the blocks. Thus, in the LSI of this type, the blocks have respective sizes which are equal to one another.
However, even with the LSI of the structure mentioned above, it is expected that attempt for equalization of clock delay times among the blocks will encounter difficulty which becomes more serious in the not far distant future.
More specifically, the delay times involved in the clock transfers from the intra-block distribution circuitry to the individual flip-flops depend on the driving capability of the distribution circuitry and capacitances of the interconnecting wires. Besides, in the case where the clock drivers are interposed between the distribution circuitry and the flip-flops, the delay depends on the driving capability of the drivers as well.
When the size of the LSI chip increases in the future, variance in the delay in the clock transfer will become more remarkable in dependence on the locations of the intra-block clock distribution circuitries, the drivers and the wires in the LSI even for the same driving capabilities of the distribution circuits and the drivers as well as the same width and thickness of the wires. Among others, variance in the driving capabilities of the intra-block distribution circuitries and the drivers will play important roles in bringing about variance in the delay involved in the clock transfer, which may also result in that the delay in clock transfer differs from one to another block.
Besides, when the integrated density of the LSI increases, the same problem as elucidated above will arise for other reasons.
In an LSI chip of high integration density, there exist many other wires than those for the clock signal, wherein the former are formed in the vicinity of or in superposition to the clock transfer wires. As a result of this, stray capacitances between the clock wires and the other wires can no more be neglected. Such stray capacitances assume different values in dependence on the positions assumed by the individual wires within the LSI chip. As a consequence, the clock transfer time becomes different in dependence on the positions of the clock wires within the LSI chip even when the length and the thickness are designed to be same among the clock signal wires. Ultimately, the clock signal transfer time will differ from one to another block.
The influence of clock skew among the blocks due to the various causes or factors mentioned above will become more adverse as the period of the clock signal is further shortened or clock frequency further increases in the future.
Besides, the known techniques suffer from additional problem that great difficulty is encountered in designing the clock transfer wires in the LSI chip where the blocks have different sizes.
By way of example, there is such an LSI chip in which a variety of circuitries having different functions are included. Let's suppose, for example, an LSI chip which includes memory circuitries and various logic circuitries. In this type LSI, it is desirable from the standpoint of circuit design to make the sizes of the blocks serving as the units for supplying clocks differ in dependence on the sizes (extents) of the circuitries mentioned above. Nevertheless, according to the prior art techniques, the clock transfer wires are so designed that the lengths of the wires extending from the intra-block clock distribution circuitries to the flip-flops in the individual blocks are equal to one another even in the case of the LSI chip where the blocks have different sizes.
However, in view of easiness of design, it is desirable that the clock transfer wires having lengths differing on a block-by-block basis can be used so far as the block size differs from one to another block.
At this juncture, it should be mentioned that the influence of variance in the driving capability among the drivers can be mitigated in the case of the prior art LSI in which the mesh-like clock wiring is adopted, as described hereinbefore, because the outputs of the clock drivers arrayed in a multiplicity of stages are mutually connected. Besides, because the clock transfer wires of net-like pattern are provided over the whole chip, accurate control or adjustment of the wire length is not necessarily required.
However, because the clock transfer wiring is of mesh-like pattern, the overall length of the wire is much longer than that of the wire used in the tree-like wiring pattern. For this reason, the prior art technique mentioned above suffers a problem of large power consumption due to the wire. It goes without saying that the power consumption will further increase as the scale of the LSI becomes larger.
When compared with the prior art techniques mentioned above, it is expected that the approach disclosed in JP-A-4-76610 can ensure more effective reduction of the clock skew in the LSI. However, in reality, it is doubtful that the effect is to be satisfactory. More specifically, according to the approach as proposed, phase comparisons within the blocks and between the adjacent blocks are performed sequentially to thereby realize the phase matching of the clock for the whole chip. Consequently, errors in the sequential phase matchings will be accumulated, to thereby prevent the effect as intended from being attained.